 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| SL2524 1.3GHz Dual Wideband Logarithmic Amplifier DS4548 - 2.1 July 1995 The SL2524 is a pin compatible replacement for the SL2521 and SL2522 series of log amplifiers, and exhibits a superior stability performance. The amplifier is a successive detection type which provides linear gain and accurate logarithmic signal compression over a wide bandwidth. The two stages can be operated independently. When six stages (three SL2524s) are cascaded the strip can be used for IFs between 30-650MHz whilst achieving greater than 65dB dynamic range with a log accuracy of <1.0dB. The balanced limited output also offers accurate phase information with input amplitude. FEATURES s s s s s s 1.3GHz Bandwidth (-3dB) Balanced IF limiting 3ns Rise Times/5ns Fall Times (six stages) 20ns Pulse Handling (six stages) Temperature Stabilised Surface Mountable APPLICATIONS s s s Ultra Wideband Log Receivers Channelised Receivers Monopulse Applications OPTIONAL PIN REFERENCE ABSOLUTE MAXIMUM RATINGS Supply Voltage (VCC above VEE) +7.0V Storage temperature -65C to +150C Operating temperature range SL2524/B/LC -40C to +85C SL2524/C/HP -30C to +85C Junction temperature - LC20 +175C - HP20 +150C Applied DC voltage to RF input 0.4V (between RF I/P pins) Applied RF power to RF input +15dBm NOT less than 180 Value of RSET resistors Thermal resistance:Die to case -LC 20 28C/W - HP20 20C/W Die to ambient - LC20 73C/W - HP20 82C/W PIN 1 2 3 4 5 6 7 8 9 10 DESCRIPTION SUB VEE IF OUTPUT (A) IF OUTPUT (A) VEE (A) OUTPUT VC (A) IF INPUT (A) IF INPUT (A) VCC (A) DET. OUTPUT (A) R SET (A) PIN 11 12 13 14 15 16 17 18 19 20 DESCRIPTION N/C R SET (B) DET. OUTPUT (B) VCC (B) IF OUTPUT (B) IF OUTPUT (B) OUTPUT VCC (B) VEE (B) IF INPUT (B) IF INPUT (B) ORDERING INFORMATION SL2524/B/LC (Ceramic leadless chip carrier package) SL2524/C/HP (Plastic J lead chip carrier package) SL2524/NA/1C (DC probe tested bare die) 5962 - 92315 (SMD) Fig.1 Pin connections top view SL2524 Fig.2 Circuit diagram of single stage A - (stage B pin Nos bracketed) Fig.3 Pad map for SL2524 naked die 2 SL2524 ELECTRICAL CHARACTERISTICS - SL2524B Guaranteed at the following test conditions unless otherwise stated Frequency = 200MHz, Tamb = +25C, Input power = -30dBm, VCC = 6V 0.1V, Source Impedance = 50. Load impedance = 50, Test Circuit = Fig. 4, RSET = 300. Tested as a dual stage. Characteristic Supply current Small signal gain (dual stage, single ended) Value Min 70 9.6 10.1 9.9 9.5 9.7 9.3 8.2 Detected output current (max) 3.20 3.05 3.15 3.10 2.80 2.90 2.85 Detected output current (no signal) Upper cut off frequency (RF) 0.85 0.80 0.80 600 900 600 Lower cut off frequency (RF) Detector cut off frequency Limited IF O/P voltage Phase variation with input level (normalised to -30dBm) 135 Typ 87 11.4 11.6 11.3 11.0 11.2 10.7 9.7 3.45 3.25 3.30 3.30 3.10 3.15 3.10 0.95 0.93 0.90 1100 1100 800 0.35 700 155 02.0 -4.02.0 Limited O/P var with temp. Noise figure Max I/P before overload Input impedance Output impedance 12 14 15 1 50 175 03.0 -4.03.0 25 1 Max 100 13.0 13.1 12.7 12.5 12.7 12.1 11.2 3.70 3.45 3.45 3.50 3.30 3.45 3.65 1.15 1.10 1.10 mA dB dB dB dB dB dB dB mA mA mA mA mA mA mA mA mA mA MHz MHz MHz MHz MHz mV Degree Degree mV dB dBm k 1k in parallel with 2pF Tamb = +25C f = 25MHz See Notes 1, 3 Tamb = -40C f = 200MHz See Notes 2, 3 Tamb = +25C f = 200MHz See Note 3 Tamb = +85C f = 200MHz See Notes 2, 3 Tamb = -40C f = 500MHz See Notes 2, 3 Tamb = +25C f = 500MHz See Note 3 Tamb = +85C f = 500MHz See Notes 2, 3 Tamb = +25C, VIN = 0dBm, f = 25MHz See Note 1 Tamb = -40C, VIN = 0dBm, f = 200MHz See Note 2 Tamb = +25C, VIN = 0dBm, f = 200MHz Tamb = +85C, VIN = 0dBm, f = 200MHz See Note 2 Tamb = -40C, VIN = 0dBm, f = 500MHz See Note 2 Tamb = +25C, VIN = 0dBm, f = 500MHz Tamb = +85C, VIN = 0dBm, f = 500MHz See Note 2 Tamb = -40C, See Note 2 Tamb = +25C, See Note 2 Tamb = +85C, See Note 2 -3dB w.r.t 200MHz, Tamb = -40C See Note 2 -3dB w.r.t 200MHz, Tamb = +25C -3dB w.r.t 200MHz, Tamb = +85C See Note 2 -3dB w.r.t 200MHz, Tamb = +25C 50% O/P current w.r.t. 200MHz I/P power = 0dBm, Tamb = +25C Frequency = 70MHz, -55 to +3dBm See Note 2 Frequency = 200MHz, -55 to +3dBm See Note 2 See Note 1 Units Conditions NOTES 1. Parameter guaranteed but not tested 2. Tested at 25C only, but guaranteed at temperature 3. Gain will typically increase by 6dB, when RF outputs use 1k loads in place of 50 3 SL2524 ELECTRICAL CHARACTERISTICS - SL2524C Guaranteed at the following test conditions unless otherwise stated Frequency = 200MHz, Tamb = +25C, Input power = -30dBm, VCC = 6V 0.1V, Source Impedance = 50. Load impedance = 50, Test Circuit = Fig. 4, RSET = 300. Tested as a dual stage. Characteristic Supply current Small signal gain (dual stage, single ended) Value Min 70 9.6 9.6 9.4 9.0 9.2 8.8 7.7 Detected output current (max) 3.20 2.95 3.05 3.00 2.70 2.80 2.75 Detected output current (no signal) Upper cut off frequency (RF) Lower cut off frequency (RF) Detector cut off frequency Limited IF O/P voltage Phase variation with input level (normalised to -30dBm) 105 0.75 0.70 0.70 Typ 87 11.4 11.6 11.3 11.0 11.2 10.7 9.7 3.45 3.25 3.30 3.30 3.10 3.15 3.10 0.95 0.93 0.90 1000 0.35 600 135 02.0 -4.02.0 Limited O/P var with temp. Noise figure Max I/P before overload Input impedance Output impedance 12 14 15 1 50 25 175 2 Max 100 13.0 13.6 13.2 13.0 13.2 12.6 11.7 3.70 3.55 3.55 3.50 3.30 3.55 3.75 1.25 1.20 1.20 mA dB dB dB dB dB dB dB mA mA mA mA mA mA mA mA mA mA MHz MHz MHz mV Degree Degree mV dB dBm k 1k in parallel with 2pF Tamb = +25C f = 25MHz See Note 3 Tamb = -30C f = 200MHz See Notes 2, 3 Tamb = +25C f = 200MHz See Note 3 Tamb = +85C f = 200MHz See Notes 2, 3 Tamb = -30C f = 500MHz See Notes 1, 3 Tamb = +25C f = 500MHz See Note 1 Tamb = +85C f = 500MHz See Notes 1, 3 Tamb = +25C, VIN = 0dBm, f = 25MHz Tamb = -30C, VIN = 0dBm, f = 200MHz See Note 2 Tamb = +25C, VIN = 0dBm, f = 200MHz Tamb = +85C, VIN = 0dBm, f = 200MHz See Note 2 Tamb = -30C, VIN = 0dBm, f = 500MHz See Note 1 Tamb = +25C, VIN = 0dBm, f = 500MHz See Note 1 Tamb = +85C, VIN = 0dBm, f = 500MHz See Note 1 Tamb = -30C, See Note 2 Tamb = +25C, See Note 2 Tamb = +85C, See Note 2 -3dB w.r.t 200MHz, Tamb = +25C See Note 1 -3dB w.r.t 200MHz, Tamb = +25C 50% O/P current w.r.t. 200MHz I/P power = 0dBm, Tamb = +25C Frequency = 70MHz, -55 to +3dBm See Note 1 Frequency = 200MHz, -55 to +3dBm See Note 1 See Note 1 Units Conditions NOTES 1. Parameter guaranteed but not tested 2. Tested at 25C only, but guaranteed at temperature 3. Gain will typically increase by 6dB, when RF outputs use 1k loads in place of 50 4 SL2524 GENERAL DESCRIPTION The SL2524 is primarily intended for use in Radar and EW receivers. Six stages (3 chip carriers) can be cascaded to form a very wideband logarithmic ampifier offering >65dB of input dynamic range, with pulse handling of better than 25ns. (See figs 5 and 6.) A six stange strip also offers balanced IF limiting, linearity (log accuracy) of < 1.0dB, temperature stabilisation and programmable detector characteristics. The detector has an external resistor set (RSET) pin which allows the major characteristics of the detector to be programmed. With six stage strip it is possible to vary the value of RSET on each detector and so improve the overall log error/linearity. The detector is full wave and good slew rates are achieved with 2ns rise and 5ns fall times (no video filter). The video bandwidth of a six stage strip is typically 600MHz (-3dB). The amplifier also offers balanced IF limiting, low phase shift versus input amplitude, and at an IF of 120MHz, less than 5 of phase change is achievable over the input level of -55dBm to +5dBm. The IF and Video ports can be used simultaneously, so offering phase, frequency and pulse (video) information. A slight loss of dynamic range (2dB) will be observed when the IF ports are used in conjunction with the video. Fig.4 Test circuit Fig.5 Schematic diagram showing configuration of SD Log strip 5 SL2524 Fig.6 Circuit diagram for 6-log strip (results shown in figs. 11 to 24 were achieved with this circuit) Typical characteristics for a dual - stage amplifier (i.e. One SL2524) Fig.7 IF Gain vs frequency of 2 amplifiers (One SL2524) 6 SL2524 Typical characteristics for a dual - stage amplifier (i.e. One SL2524) cont. Fig.8 Normalised phase vs CW input level at 50, 250 and 450MHz for 50 O/P termination (25C) Fig.9 Detector current vs RSET at 200MHz (25C) 7 SL2524 Typical characteristics for a dual - stage amplifier (i.e. One SL2524) cont. Fig.10 Detector current vs frequency at RSET = 200 and 500 (25C) Typical characteristics for a six stage strip, using detected output (Ref. figs 5 & 6) Fig.11 Detector bandwidth (25C) 8 SL2524 Typical characteristics for a six stage strip, using detected output (Ref. figs 5 & 6) cont. 0 Fig.12 Detected O/P vs CW input at 60, 125, 450 and 600MHz at 25C Fig.13 Detected O/P vs CW input level and temperature at 60 and 125MHz 9 SL2524 Typical characteristics for a six stage strip, using detected output (Ref. figs 5 & 6) cont. Fig.14 Detected O/P vs CW input level at 450MHz across temperature Fig.15 Typical log linearity of detected output measured at 450MHz (25C) 10 SL2524 Typical characteristics for a six stage strip as a low phase shift wideband limiter (Ref. figs 5 & 6) Fig.16 IF limiting characteristics at 60MHz and 500MHz (25C) Fig.17 IF limiting characteristic at 60MHz across temperature 11 SL2524 Typical characteristics for a six stage strip as a low phase shift wideband limiter (Ref. figs 5 & 6) Fig.18 IF limiting characteristic at 500MHz across temperature Fig.19 Small signal gain vs frequency across temperature 12 SL2524 Typical characteristics for a six stage strip as a low phase shift wideband limiter (Ref. figs 5 & 6) Fig.20 Phase deviation vs CW input level (normalised at -30dBm) at 25C across input frequency Fig.21 Phase deviation vs CW input level (normalised at -30dBm) at 50MHz across temperature 13 SL2524 Typical characteristics for a six stage strip as a low phase shift wideband limiter (Ref. figs 5 & 6) Fig.22 Phase deviation vs CW input level (normalised at -30dBm) at 450MHz across temperature Fig.23 Peak phase deviation over -65dBm +10dBm CW input level vs CW input frequency. Across temperature 14 For more information about all Zarlink products visit our Web Site at www.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively "Zarlink") is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink. This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink's conditions of sale which are available on request. Purchase of Zarlink's I2C components conveys a licence under the Philips I2C Patent rights to use these components in and I2C System, provided that the system conforms to the I2C Standard Specification as defined by Philips. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright Zarlink Semiconductor Inc. All Rights Reserved. TECHNICAL DOCUMENTATION - NOT FOR RESALE |
Price & Availability of SL2524
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |